Ecl to ttl converter

The other differential amplifier uses a p-channel differential transistor pair to provide for the common mode input range from V SS to V DD -2 V Tp where V Tp is the absolute p-channel threshold voltage. This range covers the TTL logic common mode range, i.

Each differential pair is provided with its own input level shifters to ensure that the differential inputs namely nodes N7, N8, N9 and N10 in FIG.

Operation of the one differential amplifier in its active region provides the highest voltage gain for amplifying the low level input signals to produce CMOS output signals exhibiting a relatively large output swing. Operation of the other differential amplifier in its cutoff region eliminates a potential slow signal path, thereby boosting the timing response of the converter.

When ECL signals are input to the logic converter, the p-channel differential pair is shut off. The n-channel differential pair operates in conjunction with additional transistors to form a conventional differential transconductance amplifier. When a signal pair composed of a TTL signal and a fixed voltage input for example 1.

The p-channel differential pair operates in cooperation with additional transistors to form a conventional differential transconductance amplifier. The differential signals produced by the differential transconductance amplifier in each of the two modes of operation are converted into a single-ended rail-to-rail CMOS output signal. With the foregoing introduction, the circuit of FIG.

Whereas the portion of the circuit to the right of dashed line A in FIG. Elements that mirror one another about a vertical axis of reflection are designated by the same reference numeral followed by the lower case letters "a" and "b", respectively, whereas elements that mirror one another about a horizontal axis of reflection are differentiated by the use of a prime designation after the reference number of the element in the lower half of the figure.

For convenience, transistors 11b and 21b' have also been given the designations M5 and M6, respectively. Referring to FIG. The source electrodes of the differential transistor pair are connected in common at node N1, which is connected through n-type transistor 18 to digital ground VSS, thereby forming the "tail" of the differential transistor pair. The differential input to the differential transistor pair is applied at nodes N7 and N8.

Level shifting circuits 10a and 10b are connected to respective transistors of the differential transistor pair. Each of the level shifting circuits consists of two series-connected n-type transistors 15a, 17a; 15b, 17b. The gate electrodes of the transistors 17a and 17b, as well as the gate electrode of transistor 18, are connected to an n-transistor bias current source A p-type differential amplifier 20' includes a p-type differential transistor pair, transistors 19a' and 19b', each connected through a respective load device formed by n-type transistor 21a' and p-type transistor 21b' to a digital voltage source VSS, which may be approximately 0 V.

The source electrodes of the differential transistor pair are connected in common at node N4, which is connected through p-type transistor 26 to digital power VDD, thereby forming the "tail" of the differential transistor pair. The differential input to the differential transistor pair is applied at nodes N9 and N Level shifting circuits 10a' and 10b' are connected to respective transistors of the differential transistor pair.

Each of the level shifting circuits consists of two series-connected p-type transistors 23a', 25a'; 23b', 25b'. The gate electrodes of the transistors 25a' and 25b', as well as the gate electrode of transistor 26, are connected to a p-transistor bias current source Key components in the circuit of FIG.

Transistors M1-M4 are arranged in an inverting configuration. An invertor 35 is therefore used to produce the final output signal OUT1. In operation, the level shifting circuits 10a, 10b, 10a' and 10b' ensure that only one of the differential amplifiers 20 and 20' is turned on at a time depending on the differential input signals to the circuit. When modified ECL signals are input to the circuit, the p-channel differential pair 20' is shut off i. The n-channel differential pair 20 works with transistors M1-M3 and M6 to form a conventional differential transconductance amplifier.

Note in this regard that the gate electrode of transistor M6 is connected at node N5 to the source electrode of transistor M3, allowing transistor M6 to be "borrowed" from the differential amplifier 20' when the differential amplifier is inactive. The resulting differential transconductance amplifier is shown in FIG. Unfortunately, however, the signal processing module in which the logic level conversion circuitry is to be incorporated may not have the circuitry real estate that will accommodate the auxiliary and cost increasing power supply.

In accordance with the present invention, this problem is successfully addressed by means of an interface circuit substantially the entire portion of which operates off only the power supply bus normally carried by the module, but which performs an intermediate level conversion to a logic level window that will enable an output stage to successfully achieve the target voltage logic level parameters though a single external power connection from the adjacent downstream module.

More particularly, the present invention is directed to a circuit arrangement for interfacing first, parallel format positive polarity TTL signals e. The binary states of the ECL signals transition about a switching level of The multistage circuit arrangement includes a parallel-to-serial shift register, a first or intermediate voltage level shifting stage and an output or TTL-ECL level shifting stage, connected in cascade. The output level shifting stage is powered by the on-board TTL supply and from an external connection to the downstream CRT unit.

As a consequence, what is produced is an intermediate level quasi analog signal which transitions between reduced or intermediate high and low voltage levels at a switching level corresponding to that e.

This reduced or intermediate level TTL type signal is coupled to a second or output, TTL-ECL voltage level shifting stage, which is powered by both the internal TTL supply bus and by an external jumper connection to the downstream module to which the output ECL signals are to be supplied. The second voltage level shifting stage produces, from the intermediate TTL type signals, the desired negative polarity ECL output signals.

Referring now to FIG. Output level shifting stage 30 is powered from on-board TTL supply bus 40 and from an external connection 50 to an ECL terminal -5 volts from a downstream ECL-driven module e. CRT display unit As noted above, the multistage circuit arrangement of the present invention interfaces parallel format positive polarity TTL signals, e.

Shift register 10 converts the parallel format, 25 MHz TTL signals on link 11 into an increased data rate e. In this case, however, since the negative supply is unavailable, shift register 10 can be powered only by the TTL supply bus. Consequently, the particular component chosen for shift register 11 must be one that can be driven only by a positive supply.

For this purpose, shift register 10 may comprise a type shift register manufactured by AMD. As shown in FIG. Because ECL-configured shift stage 20 is powered by TTL supply bus 40, its response time is relatively slow at the MHz data rate of the serial data stream.

What is produced is an intermediate level quasi analog signal which transitions between reduced or intermediate high and low voltage levels at a switching level corresponding to that e. Since stage 30 is readily accessible for connection to an external power supply, specifically the -5 volt ECL supply rail of the adjacent, downstream CRT module, it is powered by both the internal TTL supply bus 40 and by an external jumper connection 50 to the CRT module to which the output ECL signals are to be supplied.

As will be appreciated from the foregoing description, the lack of circuit component real estate for providing an auxiliary DC-DC converter to serve the power level requirements of TTL-ECL conversion circuitry between successive stages of a system is successfully addressed in accordance with the present invention by means of an interface circuit substantially the entire portion of which operates off only the power supply bus normally carried by the module, but which performs an intermediate level conversion to a logic level window that will enable an output stage to successfully achieve the target voltage logic level parameters though a single external power connection from the adjacent module.

While we have shown and described an embodiment in accordance with the present invention, it is to be understood that the same is not limited thereto but is susceptible to numerous changes and modifications as known to a person skilled in the art, and we therefore do not wish to be limited to the details shown and described herein but intend to cover all such changes and modifications as are obvious to one of ordinary skill in the art.

What is claimed: 1. The emitter of the second NPN transistor is coupled to the current mirror circuit by a second resistor. The first and second resistors have equal resistance. The current mirror is connected to a second supply voltage terminal for receiving supply voltage V EE. An emitter follower transistor has a base connected to a node between the second resistor and the current mirror and provides an output signal that is referenced to supply voltage V EE. However, the current mirror portion of the circuit requires a differential input and is slow to perform the translation because of the resistive-capacitive time constant associated with the first and second resistors and the Miller capacitance of a transistor in the current mirror.

Thus, an improved ECL to TTL voltage level translator is needed having a single input to the current mirror and that provides a faster translation time. Another object of the present invention is to provide an ECL to TTL voltage level translator having a single input to a current mirror therein.

A further object of the present invention is to provide an ECL to TTL voltage level translator having a faster response time. In carrying out the above and other objects of the invention in one form there is provided a first and a second embodiment having an improved ECL to TTL voltage level translator having a reference circuit coupled between first and second supply voltage terminals and coupled to receive a data input signal, for providing a single signal referenced to the first supply voltage terminal.

An output circuit is coupled between the first and second supply voltage terminals and is coupled to receive the single signal for providing an output signal referenced to the second supply voltage terminal. A third embodiment has a reference circuit coupled between a first supply voltage terminal and a second supply voltage terminal and coupled to receive a data input signal for referencing a voltage on the first supply voltage terminal to a voltage on the second supply voltage terminal.

A voltage setting circuit is coupled between the first supply voltage terminal and the second supply voltage terminal and is coupled to the reference circuit for setting a voltage within the reference circuit. An output circuit is coupled between the first supply voltage terminal and the second supply voltage terminal and is coupled to the voltage setting circuit for providing an output voltage referenced to a voltage on the second voltage terminal and independent of variations in voltages on the first and second supply voltage terminals.

The above and other objects, features, and advantages of the present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawing.

Referring to FIG. The emitters of transistors 10 and 11 are both connected to the collector of NPN transistor Transistor 12 has a base for coupling to current source bias voltage V CS , and an emitter coupled to supply voltage terminal 13 by resistor The collectors of transistors 10 and 11 are coupled to supply voltage terminal 15 by resistors 16 and 17, respectively.

Transistors 10, 11, 12 and resistors 14, 16, 17 comprise an ECL gate driver for providing a differential output to the bases of transistors 18 and Supply voltage terminal 15 is for coupling to supply voltage V CC and supply voltage terminal 13 is for coupling to supply voltage V EE. NPN transistor 18 has its base connected to the collector of transistor 11 and its collector connected to supply voltage terminal Transistor 19 has its base connected to the collector of transistor 10 and its collector connected to supply voltage terminal The emitter of transistor 18 is coupled by resistor 21 to the collector of transistor 22 and the bases of both transistors 22 and The emitter of transistor 19 is coupled by resistor 24 to the collector of transistor 23 and the base of transistor The emitter of transistor 23 is connected to supply voltage terminal 13 and the emitter of transistor 25 is coupled to supply voltage terminal 13 by resistor The collector of transistor 25 is coupled for providing output signal I O.

Transistors 18, 22 and resistor 21 comprise a translator network for translating the voltage at the collector of transistor 11 to transistor Transistors 19, 23 and resistor 24 comprise a translator network for translating the voltage at the collector of transistor 10 to transistor Transistor 25 and resistor 26 comprise a load current generator for generating output signal I O.

The resistance of resistors 16 and 17 are made substantially equal to generate the same driver output voltages and the resistance of resistors 21 and 24 are made substantially equal. In operation, transistors 22 and 23 function as a current mirror providing equal current through resistors 21 and The voltage at the collector of transistor 11 is zero. The following equations will show that the voltage at the base of transistor 25 is V EE referenced and independent of variations in V EE.

The emitters of transistors 28 and 29 are both connected to the collector of NPN transistor Transistor 31 has a base for coupling to current source bias voltage V CS , and an emitter coupled to supply voltage terminal 32 by resistor The collector of transistor 28 is connected to supply voltage terminal 34 and the collector of transistor 29 is coupled to supply voltage terminal 34 by resistor Transistors 28, 29, 31 and resistors 33, 35 comprise a driver network for providing a single ended output to the base of transistor Supply voltage terminal 34 is for coupling to supply voltage V CC and supply voltage terminal 32 is for coupling to supply voltage V EE.